Current designs for down-converters and up-converters in satellite applications typically utilize amplifiers that use high power and have a high mass/weight, along with mixers, oscillators, and heavy filter banks. Such devices consume an undesirable amount of Size, Weight, Power, and Cost (SWaPC) and, because of the high part count, such devices have poorer than desired reliability and are difficult and time consuming to manufacture and test.
The harsh environment faced by a satellite can increase the challenge of designing electronic circuitry. One of the primary environmental risks in a satellite application is associated with the ionizing radiation environment present in space. It should be noted that radiation effects associated with ionizing radiation are also present in terrestrial applications, though the rate of occurrence in terrestrial applications is significantly lower than in space applications. The radiation environment in space includes heavy ions, protons, and neutrons which can temporarily impact the normal operation of semiconductor devices via single event effects (SEE). Additionally total ionizing dose (TID), and/or displacement damage dose (DDD) effects are caused by long-term exposure to radiation accumulated during the mission duration and impact semiconductor performance through parametric degradation including current leakage and timing shifts. Reference may be made to “Single Event Effects in Aerospace” by Edward Petersen, October. 2011. ISBN-10: 0470767499; ISBN-13: 978-0470767498, the entire contents of which may be incorporated herein in their entirety.
The effects of SEE are generally instantaneous and can impact the operation of the semiconductor circuit. These SEE effects include single event latchup (SEL), single event upset (SEU), single event transient (SET), and single event functional interrupt (SEFI). Mitigation for SEL can be provided via use of a technology such as silicon on insulator (SOI). The effects of SEU, SET, and/or SEFI can result in a serial communication line (commonly referred to as a lane) to go into an invalid state (possibly due to a loss of lock in the clock circuitry or an induced error in the control logic) in which valid data is no longer being transmitted or received for an extended period of time. The rate of occurrence of soft errors in terrestrial applications for a typical semiconductor chip design is significantly lower than the rate of occurrence of SEU, SET, and/or SEFI for the same semiconductor chip design in space applications.
It is against this background that the techniques disclosed herein have been developed.